Programmable logic arrays (PLA's) are becoming more complex and many utilize feedback into the array as part of their normal logic function. Those devices utilizing feedback require an abnormally large number of logic cycles to be run in order to provide a known feedback input into the output circuitry, so that the combination of all input signals into the array, both from feedback as well as input circuitry are known.
The testing of PLA's has become more complex with the increase in functional capability of the device. There are two methods of testing PLA's. The first is an array verify which checks to see which of the fuses have been blown in the PLA and which are still functional. This method of testing has inherent disadvantages in that the logical functioning of the device is not thoroughly tested. The second method of testing is a logical verify which applies a data set at the inputs and then through changing the data sets checks the output to determine the proper logical flow through the device. Since the number of logical inputs and outputs becomes very large with the ever increasing number of connections, inputs, and outputs of the devices, this method of testing begins to take on an inordinate amount of time to thoroughly test the logic. See T. L. Larson, et al, "Field Programmable Logic Devices" Electronic Engineering, January, 1980, p. 37 at p. 47 for a more detailed background discussion.
One method of shortening the required test time for a complete logical test is to preset the feedback circuitry at the outputs of the device with a known data high signal. Thereafter, when input is presented to the array the feedback circuits will also present known data in the form of a high signal. Another method is to use a clear function to preset the feedback circuit in the outputs with a low data signal. This is essentially the same as preset in function. They do, however, present certain limitations.
The combination of a clear option or preset high signal option would require additional pins on the device and is therefore not an optimum solution. Additionally, with a multitude of outputs having feedback circuitry, the selective use of high signals on some feedback circuitry and low signals on the remaining circuitry is not possible utilizing the clear or preset mode of operation.
Accordingly, it is an object of the present invention to provide a programmable logic array device with an enhanced testability feature, wherein the time required for a complete logical test is considerably shortened.
Another object of the present invention is to provide an optional preset or clear function within a programmable logic array device, wherein feedback circuitry at the outputs may be preloaded with a selected data signal, utilizing the same number of pin connections.